/* 
 *	Header file for the Microchip
 *	PIC 16c620 chip
 *	PIC 16c621 chip
 *	PIC 16c622 chip
 *	Midrange Microcontrollers
 */

static unsigned char TMR0	@ 0x01;
static unsigned char PCL	@ 0x02;
static unsigned char STATUS	@ 0x03;
static unsigned char FSR	@ 0x04;
static unsigned char PORTA	@ 0x05;
static unsigned char PORTB	@ 0x06;
static unsigned char PCLATH	@ 0x0A;
static unsigned char INTCON	@ 0x0B;
static unsigned char PIR1	@ 0x0C;
static unsigned char CMCON	@ 0x1F;

static unsigned char bank1	OPTION	@ 0x81;
static unsigned char bank1	TRISA	@ 0x85;
static unsigned char bank1	TRISB	@ 0x86;
static unsigned char bank1	PIE1	@ 0x8C;
static unsigned char bank1	PCON	@ 0x8E;
static unsigned char bank1	VRCON	@ 0x9F;

/*	STATUS bits	*/
static bit	TO	@ (unsigned)&STATUS*8+4;
static bit	PD	@ (unsigned)&STATUS*8+3;

/*	INTCON bits	*/
static bit	GIE	@ (unsigned)&INTCON*8+7;
static bit	PEIE	@ (unsigned)&INTCON*8+6;
static bit	T0IE	@ (unsigned)&INTCON*8+5;
static bit	INTE	@ (unsigned)&INTCON*8+4;
static bit	RBIE	@ (unsigned)&INTCON*8+3;
static bit	T0IF	@ (unsigned)&INTCON*8+2;
static bit	INTF	@ (unsigned)&INTCON*8+1;
static bit	RBIF	@ (unsigned)&INTCON*8+0;

/*	PIR1 bits	*/
static bit	CMIF	@ (unsigned)&PIR1*8+2;

/*	CMCON bits	*/
static bit	C2OUT	@ (unsigned)&CMCON*8+7;
static bit	C1OUT	@ (unsigned)&CMCON*8+6;
static bit	CIS  	@ (unsigned)&CMCON*8+3;
static bit	CM2  	@ (unsigned)&CMCON*8+2;
static bit	CM1  	@ (unsigned)&CMCON*8+1;
static bit	CM0  	@ (unsigned)&CMCON*8+0;


/* 	OPTION bits	*/
static bank1 bit	RBPU	@ (unsigned)&OPTION*8+7;
static bank1 bit	INTEDG	@ (unsigned)&OPTION*8+6;
static bank1 bit	T0CS	@ (unsigned)&OPTION*8+5;
static bank1 bit	T0SE	@ (unsigned)&OPTION*8+4;
static bank1 bit	PSA	@ (unsigned)&OPTION*8+3;
static bank1 bit	PS2	@ (unsigned)&OPTION*8+2;
static bank1 bit	PS1	@ (unsigned)&OPTION*8+1;
static bank1 bit	PS0	@ (unsigned)&OPTION*8+0;

/*	PIE1 bits	*/
static bank1 bit	CMIE	@ (unsigned)&PIE1*8+2;

/*	PCON bits	*/
static bit	POR	@ (unsigned)&PCON*8+1;	
static bit	BOR	@ (unsigned)&PCON*8+0;

/*	VRCON bits	*/
static bank1 bit	VREN	@ (unsigned)&VRCON*8+7;
static bank1 bit	VROE	@ (unsigned)&VRCON*8+6;
static bank1 bit	VRR	@ (unsigned)&VRCON*8+5;
static bank1 bit	VR3	@ (unsigned)&VRCON*8+3;
static bank1 bit	VR2	@ (unsigned)&VRCON*8+2;
static bank1 bit	VR1	@ (unsigned)&VRCON*8+1;
static bank1 bit	VR0	@ (unsigned)&VRCON*8+0;

#define CONFIG_ADDR	0x2007
#define FOSC0		0x01
#define FOSC1		0x02
#define WDTE		0x04
#define PWRTE		0x08
#define CP0		0x10
#define CP1		0x20
#define BODEN		0x40