/*
 *	Header file for the Microchip
 *	PIC 16c923 chip
 *	Midrange Microcontrollers
 */

static unsigned char TMR0	@ 0x01;
static unsigned char PCL	@ 0x02;
static unsigned char STATUS	@ 0x03;
static unsigned char FSR	@ 0x04;
static unsigned char PORTA	@ 0x05;
static unsigned char PORTB	@ 0x06;
static unsigned char PORTC	@ 0x07;
static unsigned char PORTD	@ 0x08;
static unsigned char PORTE	@ 0x09;
static unsigned char PCLATH	@ 0x0A;
static unsigned char INTCON	@ 0x0B;
static unsigned char PIR1	@ 0x0C;
static unsigned char TMR1L	@ 0x0E;
static unsigned char TMR1H	@ 0x0F;
static unsigned char T1CON	@ 0x10;
static unsigned char TMR2	@ 0x11;
static unsigned char T2CON	@ 0x12;
static unsigned char SSPBUF	@ 0x13;
static unsigned char SSPCON	@ 0x14;
static unsigned char CCPR1L	@ 0x15;
static unsigned char CCPR1H	@ 0x16;
static unsigned char CCP1CON	@ 0x17;

	/*  Bank 1  */
static unsigned char bank1	OPTION	@ 0x81;
static unsigned char bank1	TRISA	@ 0x85;
static unsigned char bank1	TRISB	@ 0x86;
static unsigned char bank1	TRISC	@ 0x87;
static unsigned char bank1	TRISD	@ 0x88;
static unsigned char bank1	TRISE	@ 0x89;
static unsigned char bank1	PIE1	@ 0x8C;
static unsigned char bank1	PCON	@ 0x8E;
static unsigned char bank1	PR2	@ 0x92;
static unsigned char bank1	SSPADD	@ 0x93;
static unsigned char bank1	SSPSTAT	@ 0x94;

	/*  Bank 2  */
static unsigned char bank2	PORTF	@ 0x107;
static unsigned char bank2	PORTG	@ 0x108;
static unsigned char bank2	LCDSE	@ 0x10D;
static unsigned char bank2	LCDPS	@ 0x10E;
static unsigned char bank2	LCDCON	@ 0x10F;
static unsigned char bank2	LCDD00	@ 0x110;
static unsigned char bank2	LCDD01	@ 0x111;
static unsigned char bank2	LCDD02	@ 0x112;
static unsigned char bank2	LCDD03	@ 0x113;
static unsigned char bank2	LCDD04	@ 0x114;
static unsigned char bank2	LCDD05	@ 0x115;
static unsigned char bank2	LCDD06	@ 0x116;
static unsigned char bank2	LCDD07	@ 0x117;
static unsigned char bank2	LCDD08	@ 0x118;
static unsigned char bank2	LCDD09	@ 0x119;
static unsigned char bank2	LCDD10	@ 0x11A;
static unsigned char bank2	LCDD11	@ 0x11B;
static unsigned char bank2	LCDD12	@ 0x11C;
static unsigned char bank2	LCDD13	@ 0x11D;
static unsigned char bank2	LCDD14	@ 0x11E;
static unsigned char bank2	LCDD15	@ 0x11F;

	/*  Bank 3  */
static unsigned char bank3	TRISF	@ 0x187;
static unsigned char bank3	TRISG	@ 0x188;

/*	STATUS bits	*/
static bit	TO	@ (unsigned)&STATUS*8+4;
static bit	PD	@ (unsigned)&STATUS*8+3;

/*	INTCON bits	*/
static bit	GIE	@ (unsigned)&INTCON*8+7;
static bit	PEIE	@ (unsigned)&INTCON*8+6;
static bit	T0IE	@ (unsigned)&INTCON*8+5;
static bit	INTE	@ (unsigned)&INTCON*8+4;
static bit	RBIE	@ (unsigned)&INTCON*8+3;
static bit	T0IF	@ (unsigned)&INTCON*8+2;
static bit	INTF	@ (unsigned)&INTCON*8+1;
static bit	RBIF	@ (unsigned)&INTCON*8+0;

/*	PIR1 bits	*/
static bit	LCDIF	@ (unsigned)&PIR1*8+7;
static bit	ADIF	@ (unsigned)&PIR1*8+6;
static bit	SSPIF	@ (unsigned)&PIR1*8+3;
static bit	CCP1IF	@ (unsigned)&PIR1*8+2;
static bit	TMR2IF	@ (unsigned)&PIR1*8+1;
static bit	TMR1IF	@ (unsigned)&PIR1*8+0;

/*	T1CON bits	*/
static bit	T1CKPS1	@ (unsigned)&T1CON*8+5;
static bit	T1CKPS0	@ (unsigned)&T1CON*8+4;
static bit	T1OSCEN	@ (unsigned)&T1CON*8+3;
static bit	T1SYNC	@ (unsigned)&T1CON*8+2;
static bit	TMR1CS	@ (unsigned)&T1CON*8+1;
static bit	TMR1ON	@ (unsigned)&T1CON*8+0;

/*	T2CON bits	*/
static bit	TOUTPS3	@ (unsigned)&T2CON*8+6;
static bit	TOUTPS2	@ (unsigned)&T2CON*8+5;
static bit	TOUTPS1	@ (unsigned)&T2CON*8+4;
static bit	TOUTPS0	@ (unsigned)&T2CON*8+3;
static bit	TMR2ON	@ (unsigned)&T2CON*8+2;
static bit	T2CKPS1	@ (unsigned)&T2CON*8+1;
static bit	T2CKPS0	@ (unsigned)&T2CON*8+0;

/*	SSPCON bits	*/
static bit	WCOL	@ (unsigned)&SSPCON*8+7;
static bit	SSPOV	@ (unsigned)&SSPCON*8+6;
static bit	SSPEN	@ (unsigned)&SSPCON*8+5;
static bit	CKP	@ (unsigned)&SSPCON*8+4;
static bit	SSPM3	@ (unsigned)&SSPCON*8+3;
static bit	SSPM2	@ (unsigned)&SSPCON*8+2;
static bit	SSPM1	@ (unsigned)&SSPCON*8+1;
static bit	SSPM0	@ (unsigned)&SSPCON*8+0;

/*	CCP1CON bits	*/
static bit	CCP1X	@ (unsigned)&CCP1CON*8+5;
static bit	CCPIY	@ (unsigned)&CCP1CON*8+4;
static bit	CCP1M3	@ (unsigned)&CCP1CON*8+3;
static bit	CCP1M2	@ (unsigned)&CCP1CON*8+2;
static bit	CCP1M1	@ (unsigned)&CCP1CON*8+1;
static bit	CCP1M0	@ (unsigned)&CCP1CON*8+0;

/*	OPTION bits	*/
static bit	RBPU	@ (unsigned)&OPTION*8+7;
static bit	INTEDG	@ (unsigned)&OPTION*8+6;
static bit	T0CS	@ (unsigned)&OPTION*8+5;
static bit	T0SE	@ (unsigned)&OPTION*8+4;
static bit	PSA	@ (unsigned)&OPTION*8+3;
static bit	PS2	@ (unsigned)&OPTION*8+2;
static bit	PS1	@ (unsigned)&OPTION*8+1;
static bit	PS0	@ (unsigned)&OPTION*8+0;

/*	PIE1 bits	*/
static bit	LCDIE	@ (unsigned)&PIE1*8+7;
static bit	ADIE	@ (unsigned)&PIE1*8+6;
static bit	SSPIE	@ (unsigned)&PIE1*8+3;
static bit	CCP1IE	@ (unsigned)&PIE1*8+2;
static bit	TMR2IE	@ (unsigned)&PIE1*8+1;
static bit	TMR1IE	@ (unsigned)&PIE1*8+0;

/*	PCON bit	*/
static bit	POR	@ (unsigned)&PCON*8+1;

#define CONFIG_ADDR	0x2007
#define FOSC0		0x01
#define FOSC1		0x02
#define WDTE		0x04
#define PWRTE		0x08
#define CP0		0x10
#define CP1		0x20