PIC16CXX Instruction Set The PIC16CXX instruction set consists of 36 instructions, each a single 14-bit wide word. Most instructions operate on a file register, f, and the working register, W (accumulator). The result can be directed either to the file register or the W register or to both in the case of some instructions. A few instructions operate solely on a file register (BSF for example). All instructions execute in a single instruction cycle unless otherwise noted. Any unused opcode is executed as a NOP. The instruction set is highly orthogonal and is grouped into three basic catagories: ù Byte Oriented operations ù Bit Oriented Operations ù Literal and Control Operations The following tables list the instructions recognized by the MPASM assembler. TABLE 14: PIC16CXX BYTE ORIENTED FILE REGISTER OPERATIONS Binary Hex Mnemonic Description 00 0111 dfff ffff 07ff ADDWF f,d Add W and f 00 0101 dfff ffff 05ff ANDWF f,d AND W and f 00 0001 1fff ffff 018f CLRF f Clear f 00 0001 0xxx xxxx 0100 CLRW Clear W 00 1001 dfff ffff 09ff COMF f,d Complement f 00 0011 dfff ffff 03ff DECF f,d Decrement f 00 1011 dfff ffff 0Bff DECFSZ f,d Decrement f, skip ifzero 00 1010 dfff ffff 0Aff INCF f,d Increment f 00 1111 dfff ffff 0Fff INCFSZ f,d Increment f, skip if zero 00 0100 dfff ffff 04ff IORWF f,d Inclusive OR W and f 00 1000 dfff ffff 08ff MOVF f,d Move f 00 0000 1fff ffff 008f MOVWF f Move W to f 00 0000 0xx0 0000 0000 NOP No operation 00 1101 dfff ffff 0Dff RLF f,d Rotate left f 00 1100 dfff ffff 0Cff RRF f,d Rotate right f 00 0110 dfff ffff 02ff SUBWF f,d Sutract W from f 00 1110 dfff ffff 0Eff SWAPF f,d Swap haves f 00 0110 dfff ffff 06ff XORWF f,d Exclusive OR W and f TABLE 15: PIC16CXX BIT ORIENTED FILE REGISTER OPERATIONS Binary Hex Mnemonic Description 01 00bb bfff ffff 1bff BCF f,b Bit clear f 01 01bb bfff ffff 1bff BSF f,b Bit set f 01 10bb bfff ffff 1bff BTFSC f,b Bit test, skip if clear 01 11bb bfff ffff 1bff BTFSS f,b Bit test, skip if set TABLE 16: PIC16CXX LITERAL AND CONTROL OPERATIONS Binary Hex Mnemonic Description 11 111x kkkk kkkk 3Ekk ADDLW k Add literal to W 11 1001 kkkk kkkk 39kk ANDLW k And literal and W 10 0kkk kkkk kkkk 2kkk CALL k Call subroutine 00 0000 0110 0100 0064 CLRWDT Clear watch dog timer 10 1kkk kkkk kkkk 2kkk GOTO k Goto address k 11 1000 kkkk kkkk 38kk IORLW k Incl. OR literal and W 11 00xx kkkk kkkk 30kk MOVLW k Move Literal to W 00 0000 0110 0010 0062 OPTION Load OPTION register W 00 0000 0000 1001 0009 RETFIE Return from Interrupt 11 01xx kkkk kkkk 34kk RETLW k Return with literal in W 00 0000 0000 1000 0008 RETURN Return from subroutine 00 0000 0110 0011 0063 SLEEP Go into stand by mode 11 110x kkkk kkkk 3Ckk SUBLW k Subtract W from literal 00 0000 0110 0fff 006f TRIS f Tristate port f 11 1010 kkkk kkkk 3Akk XORLW k Exclusive OR literal and W PIC16CXX Notes 1. TRIS and OPTION instructions are included in the instruction set for upward compatability with the PIC16C5X products. Microchip strongly recommends not using these instructions for new code development. Instead of using these instructions, directly address the TRIS and OPTION registers to obtain equivalent control. These instructions may not be supported in future PIC16CXX products. 2. When an I/O register is modified as a function of itself (i.e. MOVF 6,1) the value used will be the value present on the pins themselves. For example, a tristated pin with data latch "1" but is driven low by an external device will be relatched in the low state. 3. If this instruction is executed on file register f1 (and, where applicable d=1), the prescaler will be cleared if assigned to the RTCC. ------------ ------------------------------------------------------ PIC16CXX.INC ------------- ; There is one group of defines that is valid for all microcontrollers. ; Each microcontroller in this family also has its own section of special ; defines. Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16C71 ; 2. LIST directive in the source file ; LIST P=16C71 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Generic Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' ;----- INTCON Bits (except ADC/Periph) ------------------------------------ GIE EQU H'0007' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;========================================================================== ; ; Processor-dependent Definitions ; ;========================================================================== IFDEF __16C84 ;----- Register Files -------------------------------------------------- EEDATA EQU H'0008' EEADR EQU H'0009' EECON1 EQU H'0088' EECON2 EQU H'0089' __MAXRAM H'0AF' __BADRAM H'07', H'030'-H'07F', H'087' #define __CONFIG_0 ENDIF